6-34
Document Revision History
SV51007
2014.01.10
Document Revision History
Date
January 2014
June 2013
May 2013
Altera Corporation
Version
2014.01.10
2013.06.21
2013.05.06
Changes
? Updated the statement about setting the phase of the clock in relation
to data in the topic about transmitter clocking.
? Updated the figure that shows the phase relationship for the external
PLL interface signals.
? Clarified that "one row of separation" between two groups of DPA-
enabled channels means a separation of one differential channel.
? Clarified that "internal PLL option" refers to the option in the ALTLVDS
megafunction.
? Updated the topic about emulated LVDS buffers to clarify that you can
use unutilized true LVDS input channels (instead "buffers") as emulated
LVDS output buffers.
Updated the figure about data realignment timing to correct the data pattern
after a bit slip.
? Moved all links to the Related Information section of respective topics
for easy reference.
? Added link to the known document issues in the Knowledge Base.
? Removed all references to column and row I/Os. Stratix V devices have
I/O banks on the top and bottom only.
? Changed the color of the transceiver blocks in the high-speed differential
I/O location diagram for clarity.
? Updated the pin placement guidelines section to add figures and new
topic about using DPA-disabled differential channels.
? Added a topic about emulated LVDS buffers.
? Edited the topic about true LVDS buffers.
? Added a topic that lists the SERDES I/O standards support and the
respective Quartus II assignment values.
? Corrected the outclk2 waveform in Figure 6-4 to show -18° phase shift
(as labeled).
? Clarified that the programmable V OD assignment value of "0" is also
applicable for mini-LVDS.
? Updated the data realignment timing figure to improve clarity.
? Updated the receiver data realignment rollover figure to improve clarity.
High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
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